Taiwan - Delayed Quote • TWD Andes Technology Corporation (6533.TW) Follow Compare 405.00 -5.00 (-1.22%) As of 10:46:56 AM GMT+8. Market Open. All News Press Releases SEC Filings All SEC Filings Corporate Changes & Voting Matters Periodic Financial Reports Proxy Statements Tender Offer/Acquisition Reports Offering Registrations Andes Technology Partners with ProvenRun to Strengthen RISC-V Trusted Execution Environment Taipei, Taiwan, Dec. 18, 2024 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533), the leading supplier of RISC-V processor IP, and ProvenRun, the leading secure OS vendor for connected vehicles and smart devices, announce their partnership to offer ProvenRun’s formally proven Secure OS and Trusted Execution Environment (TEE) on Andes’ RISC-V processors. As security threats increase, device and data protection is critical for consumers and governments alike. Preventing information leak Jmem Tek and Andes Technology Partner on the World’s First Quantum-Secure RISC-V Chip Hsinchu, Taiwan, Dec. 12, 2024 (GLOBE NEWSWIRE) -- Jmem Tek, a specialist in hardware security and post-quantum cryptography for IoT devices, announces a global partnership with Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor IPs and Founding Premier member of RISC-V International. Jmem Tek also joined the AndeSentry™ security collaborative framework, which offers a range of security solutions for Andes RISC-V processors, designed to counter threats HighTec C/C++ Compiler Suite Supports Andes’ ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications Saarbrücken, Germany, Nov. 28, 2024 (GLOBE NEWSWIRE) -- HighTec EDV-Systeme GmbH, a leading provider of automotive compiler solutions, has announced support for Andes’ RISC-V IP in its highly optimized C/C++ compiler for the automotive market. This support marks a milestone for automotive software developers, as HighTec's compiler now seamlessly supports the Andes’ functional safety certified RISC-V cores to ensure optimized code generation for automotive processors, improving efficiency and per Andes Technology Collaborates with Lauterbach to Deliver RISC-V Trace Solution HSINCHU, TAIWAN, Nov. 26, 2024 (GLOBE NEWSWIRE) -- Lauterbach, the leading provider of development tools for embedded systems, and Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of RISC-V processor IP, today proudly announce their collaboration that enhances the debugging and tracing experience for engineers using Andes’ advanced NCETRACE200 trace IP with Lauterbach’s industry leading development tools TRACE32®. With the growing demand for RI Fractile licenses Andes Technology’s RISC-V vector processor as it builds radical new chip to accelerate AI inference San Jose, CA, Oct. 22, 2024 (GLOBE NEWSWIRE) -- Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, are proud to announce a partnership with Fractile, the company building the chips and systems needed to reach the next frontier of AI performance. Fractile is developing AI inference accelerators based on in-memory compute and aim to be able to run frontier AI models – large language, vision and au DeepComputing and Andes Technology Partner to Develop the World's First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop San Jose, CA, Oct. 22, 2024 (GLOBE NEWSWIRE) -- DeepComputing, a pioneer in RISC-V innovation, today announced a strategic partnership with Andes Technology Corporation, a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores. Together, the two companies collaborate to develop the world’s first RISC-V AI PC, powered by Andes’ 7nm QiLai SoC. This innovated low-power PC will come equipped with Ubuntu Desktop and aims to redefine AI computing by combining industry-leading Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification Hsinchu, Taiwan, Oct. 22, 2024 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, proudly announces the launch of its industry-leading functional safety RISC-V processor AndesCore™ D45-SE, targeting ISO 26262 ASIL-D (Automotive Safety Integrity Level D) certification. The D45-SE, derived from the production-prove Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension Hsinchu, Taiwan, Oct. 21, 2024 (GLOBE NEWSWIRE) -- Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the AndesCore™ 46-series processor family with 4 members. The first member, AX46MPV, a new 64-bit multicore superscalar vector processor IP, is the third generation of the award-winning Andes Vector core. While it maintains the same 8-stage dual-issue pipeline as its predecessor Andes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android Hsinchu, Taiwan, Oct. 18, 2024 (GLOBE NEWSWIRE) -- Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the AndesCore™ AX66 out-of-order superscalar multicore processor IP supporting the RVA23 profile. The AX66 is the 2nd member of the high-performance out-of-order AX60 series. Built on the success of the AX65 with the same 13-stage pipeline, 4-wide decode, and 8-wide out-of-order Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel San Jose, CA, June 06, 2024 (GLOBE NEWSWIRE) -- RISC-V: Shaping the Future of AI/ML, Application Processors, Automotive, and Security San Jose, CA — Jun 6, 2024 — Andes Technology (TWSE: 6533), the leading vendor in high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, unveils its agenda of the annual ANDES RISC-V CON on June 11th at the San Jose Airport DoubleTree Hotel. This year’s theme, “ANDES RISC-V CON: Deep Dive into Automotive/ Rain AI Unveils Andes Technology as Its RISC-V Partner San Francisco, CA , June 03, 2024 (GLOBE NEWSWIRE) -- Rain AI Licenses Andes AX45MPV and Taps Andes Custom Computing BU to Accelerate Its Launch of Groundbreaking Compute-In-Memory (CIM) Generative AI Solutions San Francisco, CA, June 03, 2024 - Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announces that Rain AI, a pioneer in compute-in-memory (CIM) technology, licensed Andes’ AX45MPV RISC- Andes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption SANTA CLARA, CA , May 22, 2024 (GLOBE NEWSWIRE) -- Highlights: Andes Technology and Arteris partnership aims to support the growing adoption of RISC-V SoCs by mutual customers. Focus is on high-performance/low-power RISC-V-based designs across a wide range of markets, including consumer electronics, communications, industrial applications and AI.The collaboration showcases integrated and optimized solutions with leading Andes RISC-V processor IPs and Arteris interconnect IP in silicon. CAMPBELL, Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem Hsinchu, Taiwan, May 15, 2024 (GLOBE NEWSWIRE) -- Andes, HiRain, and HPMicro jointly announced that the three parties will cooperate to combine the AndesCoreTM RISC-V processor series, the HPMicro HPM6200 full line of products, and the HiRain Vehicle OS software platform solutions to jointly build the RISC-V ecosystem in the field of automotive electronics. In this cooperation, HiRain’s AUTOSAR product INTEWORK-EAS will be adapted to HPMicro’s full line of HPM6200 products, supporting MCAL softw TASKING and Andes announce FuSa compliant Compiler support for Andes RISC-V ASIL Compliant Automotive IP To enable SoC design teams and Automotive software developers to build optimized and certifiable software solutions.Munich, Germany, March 27, 2024 (GLOBE NEWSWIRE) -- TASKING proudly announces that its ISO 26262 (functional safety) and ISO/SAE 21434 (cybersecurity) compliant compilers now fully support the Andes FuSa certified RISC-V IP. This advancement expands TASKING's RISC-V tool suite to include compilation, debugging, performance tuning, timing, and coverage analysis tools, providing a co Seven Years of Uninterrupted Growth: Andes Technology Achieves Milestone Annual Revenue Exceeding NT$1 Billion Andes Technology Is the Number One Provider of RISC-V CPU IP According to the SHD Marketing Report SHD Graphic Andes has secured an impressive 30% market share of RISC-V based chip shipping volume through its worldwide customers and is the number one provider of RISC-V CPU IP. Hsinchu, Taiwan , March 20, 2024 (GLOBE NEWSWIRE) -- Since its IPO in 2017, Andes Technology (TWSE:6533) has established itself as a leader in the CPU IP sector, achieving a fivefold increase in sales over the past seven y Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCoreTM AX45MPV Aachen, Germany and Hsinchu, Taiwan, Feb. 27, 2024 (GLOBE NEWSWIRE) -- MachineWare GmbH and Andes Technology (TWSE:6533), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announce an exciting new chapter in their collaboration, marked by a strategic partnership. This synergistic alliance is geared towards the highly innovative AndesCore™ AX45MPV, a cutting-edge multi-core RISC-V vector processor tailored for AI Andes Technology and MetaSilicon Collaborate to Build the World’s First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC Hsinchu Taiwan, Feb. 22, 2024 (GLOBE NEWSWIRE) -- RISC-V IP vendor Andes Technology and edge computing chip provider MetaSilicon jointly announced that the MetaSilicon MAT Series is the world's first automotive-grade CMOS image sensor series using RISC-V IP SoC, using Andes' AndesCore™ N25F-SE processor. They are designed in accordance with the ISO26262 functional safety standard to achieve ASIL-B level and follow the AEC-Q100 Grade 2 to achieve a high level of safety and reliability. And by usi Performance Overview Trailing total returns as of 1/9/2025, which may include dividends or other distributions. Benchmark is TSEC CAPITALIZATION WEIGHTED ST Return 6533.TW TSEC CAPITALIZATION WEIGHTED ST YTD -0.25% +0.53% 1-Year -14.01% +32.66% 3-Year -11.73% +28.30%