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TSMC Unveils Next-Generation A14 Process at North America Technology Symposium

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Showcasing TSMC’s latest offerings for high performance computing, smartphone, automotive, and IoT applications

SANTA CLARA, Calif., April 23, 2025--(BUSINESS WIRE)--TSMC (TWSE: 2330, NYSE: TSM) today unveiled its next cutting-edge logic process technology, A14, at the Company’s North America Technology Symposium. Representing a significant advancement from TSMC’s industry-leading N2 process, A14 is designed to drive AI transformation forward by delivering faster computing and greater power efficiency. It is also expected to enhance smartphones by improving their on-board AI capabilities, making them even smarter. Planned to enter production in 2028, the current A14 development is progressing smoothly with yield performance ahead of schedule.

Compared with the N2 process, which is about to enter volume production later this year, A14 will offer up to 15% speed improvement at the same power, or up to 30% power reduction at the same speed, along with more than 20% increase in logic density. Leveraging the Company’s experience in design-technology co-optimization for nanosheet transistor, TSMC is also evolving its TSMC NanoFlex™ standard cell architecture to NanoFlex™ Pro, enabling greater performance, power efficiency and design flexibility.

"Our customers constantly look to the future, and TSMC’s technology leadership and manufacturing excellence provides them with a dependable roadmap for their innovations," said TSMC Chairman and CEO Dr. C.C. Wei. "TSMC’s cutting-edge logic technologies like A14 are part of a comprehensive suite of solutions that connect the physical and digital worlds to unleash our customers’ innovation for advancing the AI future."

In addition to A14, TSMC also debuted new logic, specialty, advanced packaging and 3D chip stacking technologies, each contributing to broad technology platforms in High Performance Computing (HPC), Smartphone, Automotive, and Internet of Things (IoT). These offerings are designed to equip customers with a comprehensive suite of interconnected technologies to drive their product innovations. They include:

High Performance Computing

TSMC continues to advance its Chip on Wafer on Substrate (CoWoS®) technology to address AI’s insatiable need for more logic and high-bandwidth memory (HBM). The company plans to bring 9.5 reticle size CoWoS to volume production in 2027, enabling integration of 12 HBM stacks or more in a package together with TSMC’s leading-edge logic technology. After showcasing its revolutionary System-on-Wafer (TSMC-SoW™) technology in 2024, TSMC followed up with SoW-X, a CoWoS-based offering to create a wafer-sized system with computing power 40X the current CoWoS solution. Volume production is scheduled for 2027.