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SAN DIEGO, CA--(Marketwired - Mar 15, 2017) - Gopher Protocol Inc. (OTCQB: GOPH) ("Gopher" and the "Company"), a development-stage company, which specializes in the development of real-time, heuristic-based mobile technologies, and its partner, Alpha EDA, LLC ("Alpha"), announce today the completion of development of its software package "SIGMA EDA" ("Sigma") -- a tool that checks and corrects electrical connectivity mismatches in an integrated circuit, custom layout block. The tool reads an IC Layout Block, its Netlist and automatically corrects all connectivity mismatches. In addition, the tool provides a layout performance and DFM structural improvements by optimizing polygonal connectivity.

Nanometer designs contain millions of devices and operate at very high frequencies. To meet the challenges posed by such large-scale circuits, techniques have been developed to represent integrated circuit designs at various levels of abstraction. According to these techniques, an integrated circuit design may be represented by an electrical schematic containing devices and nets interconnecting the devices and by geometric layout data that describes patterns of regions or elements to be formed in and/or on an integrated circuit substrate (e.g., wafer). Techniques for managing highly integrated circuit designs include hierarchical design techniques. These hierarchical techniques can be essential to the efficient performance of computer-assisted integrated circuit design verification. Such verification may include operations to perform layout versus schematic comparison (LVS) using computer-based design tools.

Today, any mismatches are corrected manually by a layout designer. The layout designer first must find the correct connection and then determine how to create the correct electrical connection in the mask layout database. This process of adding/modifying an electrical connection(s) may take several hours or days to complete. Furthermore, the layout designer may introduce design rule errors in the mask layout database when adding the new connection. Eliminating the design rule errors may additionally require several more hours or days and thus, increase the design time for the integrated circuit furthermore. Using Sigma these electrical connection mismatches are automatically eliminated within minutes which results in a massive reduction in the entire chip design time. In addition, the tool includes an Auto-Correct option to automatically correct a completed IC layout block. One of the key advantages of the software is its statistical analysis and violations mapping feature. The program prepares violation statistics including a detailed report of each violation and an automatic correction solution(s). Upon user's approval, Sigma automatically corrects the violation(s), saving hours or days of manual work. After the correction, Sigma rechecks the microchip block to verify that all violations are fixed.