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DesignCon Unveils 2025 Award Winners for Best Paper Awards and Engineer of the Year

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SANTA CLARA, CA / ACCESS Newswire / March 6, 2025 / DesignCon, the premiere event for chip, board and systems design engineers, announces the 2025 Engineer of the Year, honoring excellence in engineering and new product advancements at the chip, board or system level and the winners of the prestigious 2025 Best Paper Award, recognizing exceptional contributions to the educational goals of the DesignCon program.

The 2025 DesignCon "Engineer of the Year" is Ben Dannan, founder and chief technologist, Signal Edge Solutions, a service dedicated to bridging the gap between signal integrity, a measure of the quality of an electrical signal, and power integrity, electronic engineering efforts aimed at ensuring that power supply subsystems support the performance of an entire electronic system. Before starting Signal Edge Solutions, Dannan spent time at Northrop Grumman, Bosch Security Systems and Diversey. Dannan has strong ties to DesignCon as Technical Program Committee member, Best Paper Award Winner in 2024 and 2020 and 40 Under 40 winner in 2024.

"For 30 years, DesignCon has been the premier event where we celebrate both the cutting-edge innovations shaping our future and the exceptional contributions that have brought us to where we are today," says Suzanne Deffree, Group Event Director, Informa Markets Engineering. "All recipients push the boundaries of what's possible and inspire the next generation of engineers. The dedication and innovative spirit of professionals are the driving forces behind the advancements that define our industry and fuel the progress of modern technology."

DesignCon Best Paper Awards honor outstanding contributions to the educational goals of the DesignCon program and acknowledge the authors as leading practitioners in semiconductor and electronic design.

The 2025 Best Paper Winners:

400G+ Electrical Pathfinding, authors from AMD.

Balancing Current Density to High-Power ASICs in Lateral Power Delivery Designs, Brian Hostetler, HPE Inc.

Beyond 200G: Brick Walls of 400G Links per Lane, authors from Samtec, University of L'Aquila and Keysight Technologies.

Foundational Model Approach for SI/PI Analysis Using Large Language Model Techniques, authors from Hewlett Packard Enterprise.

Low Latency Speculative Error Correction Using Simplified ML Detector for 64Gbps Wireline Transceiver, authors from Cadence Design Systems.

Next Generation 224 Gbps-PAM4 Linear: Host TX/RX, Electrical/Optical Channel Characteristics, and End-to-End Link Simulation and Analysis, authors from Intel and Semtech.