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Cadence Design Systems, Inc. CDNS has announced an expansion of its long-standing collaboration with Taiwan Semiconductor Manufacturing Company (“TSMC”), aimed at accelerating time to silicon for advanced-node and 3D-IC technologies. This enhanced partnership leverages certified design flows, silicon-proven IP and ongoing technical collaboration to drive innovation across TSMC’s most advanced process technologies, including N2P, N3 and N5 nodes.
Cadence has been delivering artificial intelligence (AI)-driven design solutions that support a range of applications, from chiplets and system-on-chips (SoCs) to advanced packaging and 3D-ICs, as a key IP provider for TSMC’s N2P, N3 and N5 platforms. The collaboration includes certified tools and flows for TSMC’s N2P and A16 nodes, with a path forward for the upcoming A14 node. Cadence is also deepening its support for TSMC’s 3DFabric technology, enhancing design and packaging possibilities. Additionally, tool certification has been extended to the newly introduced TSMC N3C process, building on existing N3P design solutions.
Cadence is advancing chip design through certified tools and optimized IP for TSMC’s N2P and A16 processes. It continues to lead in memory IP with TSMC9000 pre-silicon-certified DDR5 12.8G IP for N2P. Cadence’s digital, custom/analog and thermal analysis tools are certified for both N2P and A16 nodes. The company is also integrating large language models (LLMs) into digital design flows, enhancing automation and efficiency for future process nodes.
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In the 3D-IC space, Cadence offers a comprehensive chiplet design and packaging solution for TSMC’s 3DFabric. The company is expanding its IP portfolio for AI training applications with TSMC9000-certified 3D-IC IP, including HBM3E 9.6G in N5/N4P and pre-silicon HBM3E 10.4G in N3P, as well as UCIe 16G N3P solutions. Cadence’s HBM4 test chip is also pre-silicon-ready for tapeout, paving the way for future CoWoS-L solutions.
The Cadence Integrity 3D-IC Platform has been enhanced to deliver improved quality of results (QoR), with reference flows for 3Dblox and support for chip-package co-design, global resource optimization and advanced multiphysics analysis. New features include AI-powered planning, partitioning, optimization and automated feedthrough creation for multi-chiplet systems.
Cadence’s Sigrity X technologies and Clarity 3D Solver, integrated with the Integrity 3D-IC Platform to enable compliance automation for 3Dblox Signal and Power Integrity (SIPI) support this 3D-IC ecosystem. This integration streamlines S-parameter extraction and time-domain analysis for UCIe and HBM channels. The Cadence EMX Planar 3D Solver is certified for TSMC’s N3 node and is undergoing N2P certification to meet advanced-node IC demands.