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Aachen, Germany and Hsinchu, Taiwan, Feb. 27, 2024 (GLOBE NEWSWIRE) -- MachineWare GmbH and Andes Technology (TWSE:6533), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announce an exciting new chapter in their collaboration, marked by a strategic partnership. This synergistic alliance is geared towards the highly innovative AndesCore™ AX45MPV, a cutting-edge multi-core RISC-V vector processor tailored for AI workload acceleration and the application level. In this joint effort, MachineWare lends its support by seamlessly integrating the AX45MPV into their SIM-V high-performance simulation solution. This integration proves invaluable for software developers, enabling them to efficiently handle intricate AI and Linux stack related workloads. The result is a platform that streamlines development, testing, and software verification well in advance of physical prototypes emerging from the fabrication process. This partnership underscores the mutual commitment of MachineWare and Andes Technology to advancing processor technology.
Introducing SIM-V, an offering from MachineWare that holds immense value for developers in the RISC-V landscape. With SIM-V, developers gain the power to thoroughly test and verify their RISC-V-based systems and software applications long before first prototypes are back from the fab. At its core, SIM-V provides a fast Instruction Set Simulator (ISS) that supports all RISC-V standard extensions. One of SIM-V's notable strengths is its user-friendly customizability. Through a straightforward extension SDK, developers can swiftly integrate custom instructions, registers, and other elements into the simulator to get instant feedback on their design choices. What makes SIM-V truly special is its SystemC TLM-2.0 integration. This unique combination empowers users to seamlessly introduce their IP models into full system simulation environments, enhancing the versatility of the platform.
The AndesCore™ AX45MPV is a 64-bit 8-stage dual-issue multicore RISC-V vector processor. It incorporates RISC-V GCBP* (*P is a draft version) extensions, and supports SMP Linux with MMU (Memory Management Unit) and up to 48-bit virtual addresses. In addition, it can be configured to up to eight cores with a cache coherence manager and up to 8MB shared L2 cache memory in a cluster. The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0. It supports configurations of up to 1024-bit vector width (VLEN) and datapath width (DLEN). The AX45MPV is excellent for computations involving large arrays of data such as computer vision, digital signal processing, image processing, machine/deep learning, and scientific computing.