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San Jose, CA, June 06, 2024 (GLOBE NEWSWIRE) -- RISC-V: Shaping the Future of AI/ML, Application Processors, Automotive, and Security
San Jose, CA — Jun 6, 2024 — Andes Technology (TWSE: 6533), the leading vendor in high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, unveils its agenda of the annual ANDES RISC-V CON on June 11th at the San Jose Airport DoubleTree Hotel. This year’s theme, “ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends,” promises an exhilarating journey into the RISC-V advancements. With over 300 registered attendees, this conference is set to be an industry luminary event, bringing together top-tier experts, researchers, and industry leaders for riveting discussions and groundbreaking insights.
The ANDES RISC-V CON boasts an exceptional lineup of presentations and two dynamic panels featuring key players in the RISC-V ecosystem. The AI panel, moderated by Dylan Patel, Chief Analyst at SemiAnalysis, includes Charlie Cheng from Andes Technology, Chris Walker from Untether AI, Jim Keller from Tenstorrent, and Raja Koduri from Mihira AI. This session will dive deep into “How Open-Source is Transforming AI and Hardware”. Another highlight is the Application Processing panel, moderated by Mark Himelstein, and with panelists consisting of Barna Ibrahim from RISE, Charlie Su from Andes Technology, Lars Bergstrom from Google, and Sandro Pinto from OSYX Technologies. This session will dive deep into how RISC-V eco-system aims at helping RISC-V processor to be used as application processor in a rich OS system, including Android and the others.
The event kicks off at 9:30 AM with a welcome address from Andes Technology’s Chairman and CEO, Frankwell Lin about the RISC-V market outlook, followed with a keynote by Dr. Charlie Su, President & CTO of Andes Technology, titled “Unlocking RISC-V’s Potential in Intelligent Application Processing.” From application processors to AI/ML accelerators, Dr. Su will first give an update on market adoption for RISC-V and show a couple examples of large-scale AI/ML SoCs adopting Andes AI/ML solutions. He will also explore the high-end processor usage scenarios. Marc Evans, Director of Business Development & Marketing at Andes, will discuss Andes' automotive and security solutions.
The exhibition will display a plethora of exciting RISC-V technologies, including the Andes Qilai testchip, a high-performance SoC with a quad-core RISC-V AX45MP cluster and an NX27V vector processor, designed to accelerate the development and porting of large RISC-V applications. Additionally, there will be an automotive-grade CMOS image sensor demo using the ISO 26262 fully-compliant AndesCore™ N25F-SE by MetaSilicon. Other demos featuring Andes RISC-V cores include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan; the IT9836 TDDI demo board from ITE; the PC802SCB 5G small cell reference design from Picocom; and a Bluetooth development kit from Telink.